The present invention relates to the field of computer systems. More specifically, the present invention relates to an arbitration scheme between multiple bus agents
In addition to including a host bus and a memory bus, many computer systems include an Industry Standard Architecture (xe2x80x9cISAxe2x80x9d) bus, a Peripheral Component Interconnect (xe2x80x9cPCIxe2x80x9d) bus, or both an ISA and a PCI bus. Peripheral or memory devices that are compatible with the ISA bus may be coupled to the computer system through the ISA bus while peripheral or memory devices that are compatible with the PCI bus may be coupled to the computer s stem through the PCI bus. Typically, the devices coupled to a bus are referred to as bus agents. A bus agent may be a bus master (i.e., a bus agent that initiates a bus transaction) or a target agent (i.e., a bus agent that is the target of the bus transaction initiated by the bus master agent). When a PCI bus is added to a system that already includes an ISA bus, the PCI bus may be referred to as an intermediate or local bus. As more buses are added to a computer system, a more complex arbitration scheme may need to be implemented in order to maintain system coherency.
FIG. 1 illustrates a computer system 100 that includes an ISA Bus 108. The central processing unit 101 (xe2x80x9cCPUxe2x80x9d) is coupled to the Host-to-ISA (xe2x80x9cHost-ISAxe2x80x9d) Bridge 102 , via the Host Bus 106, and the Main Memory 103 is coupled to the Host-ISA Bridge 102 via the Memory Bus 105. The Host-ISA Bridge 102 includes the Arbitration Logic 104. When an ISA direct memory access (xe2x80x9cDMAxe2x80x9d) Agent, such as Agent 107, requests DMA service in order to access the Main Memory 103, the ISA DMA Agent 107 asserts the request line 113 (xe2x80x9cDREQxe2x80x9d), and subsequently, the Host-ISA Bridge 102 asserts the hold line 111 (xe2x80x9cHOLDxe2x80x9d). When the CPU 101 returns an asserted hold acknowledge line 110 (xe2x80x9cHOLDACKxe2x80x9d), the Host-ISA Bridge 102 is informed that the CPU 101 will no longer initiate cycles from the CPU 101 to the Main Memory 103 or ISA Bus 108. The Host-ISA Bridge 102 then proceeds to assert the acknowledge line 112 (xe2x80x9cDACK#xe2x80x9d) to inform the ISA DMA Agent 107 that the DMA transaction is now beginning.
The computer system 100 requires a relatively simple arbitration scheme because there are only, two possible types of mastersxe2x80x94the CPU and the ISA agents. Typically, in the computer system 100, any potential flushes (i.e., buffered writes from the CPU are transferred to their target ISA agents before granting the ISA agent bus mastership) may be performed by the Host-ISA Bridge 102. This buffering policy typically does not run into the condition where an ISA DMA Agent 107 cannot access the Main Memory 103.
On the other hand, when an intermediate bus, such as the PCI Bus 209, is interposed between the ISA Bus 214 and the CPU 201, the arbitration scheme may also be required to ensure system coherency. This type of arbitration scheme may be more complex because under certain conditions, an ISA agent may not be able to access the main memory without causing system failure conditions, such as system deadlock or system livelock. FIG. 2 illustrates a computer system 200 that includes both a PCI bus 209 and an ISA bus 214.
The Host-to-PCI (xe2x80x9cHost-PCIxe2x80x9d) Bridge 202 is coupled to the CPU 201 via the Host Bus 204 and to the Main Memory 203 via the Memory Bus 205. The Main Memory 203 may be dynamic random access memory (xe2x80x9cDRAMxe2x80x9d) for providing dynamic storage for run-time computer events. The PCI arbiter 207 and the CPU-to-PCI Buffer 208 resides within the Host-PCI Bridge 202. The PCI arbiter 207 arbitrates the use of the PCI bus 209 and the CPU-to-PCI Buffer 208 is used to buffer data writes (i.e., posted writes) from the CPU 201 which are destined for the PCI bus 209 or ISA Bus 214. Typically, the PCI agent 206 receives PCI bus mastership after the PCI agent 206 asserts the request line 223 (xe2x80x9cREQ#), and subsequently, the PCI Arbiter 207 asserts the grant line 222 (xe2x80x9cGNT#) which is received by the PCI agent 207.
The Host-PCI Bridge 202 is coupled to the PCI agents via the PCI Bus 209. For example, the PCI Master Agent 206 and the PCI Target Agent 211 may reside on the PCI Bus 209. Other PCI agents may also reside on the PCI Bus 209. The PCI Bus, 209 is referred to herein as a xe2x80x9cpre-emptiblexe2x80x9d bus because it may suspend the operation of one PCI agent when another operation from another PCI gent demands use of the PCI bus 209 to access the various system resources.
The PCI-to-ISA (xe2x80x9cPCI-ISAxe2x80x9d) Bridge 210 is coupled to the PCI Bus 209 to provide an expansion bridge for an ISA Bus 214. The ISA Bus 214 is referred to herein as a xe2x80x9cnon-pre-emptiblexe2x80x9d bus because when an ISA agent, such as the ISA DMA Agent 213, is granted access to the ISA Bus 214, the computer system locks out all other agents and all other buses, as well as the CPU 201 and the Main Memory 203, until the transaction for which the ISA agent was granted access has been entirely completed. This lock out feature of the ISA Bus 214 may be referred to as guaranteed access timing because the ISA agent is guaranteed system ownership for undefined periods of time w th guaranteed DRAM access.
The ISA Arbiter 212 may reside with the PCI-ISA Bridge 210 and may be used to arbitrate for he use of the ISA Bus 214. Various agents, such as the ISA DMA Agent 213 and the ISA Target Agent 215, may reside on the ISA Bus 214. Other ISA agents may also reside on the ISA Bus 214. Typically, the ISA DMA Agent 213 may access the Main Memory 203 after the ISA DMA Agent 213 asserts the request line 224 (xe2x80x9cDREQxe2x80x9d) and subsequently, the PCI-ISA Bridge 210 asserts the acknowledge or grant line 225 (DACK#) which is received by the ISA DMA Agent 213.
Unfortunately, when a pre-emptible bus, such as the PCI Bus 209 and a non-pre-emptible bus, such as an ISA Bus 214, are both incorporated into a compute system, failure conditions (e.g., system livelock and deadlock) may arise in which the ISA DMA Agent 213 may not be able to access the Mail Memory 203. For example, the ISA DMA Agent 213 may not access the Main Memory 203 for reads when the Host-PCI Bridge 202 is storing posted writes in the CPU-to-PCI Buffer 208. However, once the CPU-to-PCI Buffer 208 has completed all writes to the destined target agent(s), the ISA DMA Agent 213 may then access the Main Memory 203. As such, these types of failure conditions may be eliminated by providing a unique arbitration scheme between the PCI-ISA Bridge 210 and the Host-PCI Bridge 202.
Rather than incorporating the arbitration scheme that uses the PCI bus REQ# and GNT# signals as defined in the specification published by the PCI Special Interest Group in Portland, Oreg. (such as revisions 1.0 (1992) and 2.0 (1993) and 2.1 (1993)) the Host-PCI Bridge 202 and the PCI-ISA Bridge 210 may use the signals PHOLD# and PHLDA# which may be defined as PCI bus sideband signals. Typically, a sideband signal is defined as a signal that is not compliant with the PCI bus specification and is used to interconnect two or more PCI agents. In addition to providing the same functionality (i.e., request and grant) as the REQ# and GNT# signals, the PHOLD# signal and the PHLDA# signal provides the additional functionality of ensuring that the CPU-to-PCI Buffer 208 is flushed prior to granting PCI bus mastership to the PCI-ISA Bridge 210 in order to maintain system coherency. The PHOLD# and the PHLDA# signals are described below.
FIG. 3 illustrates a DMA operation requested by the ISA DMA Agent 213. The ISA DMA Agent 213 asserts the DREQ signal 304 when it is requesting data transfers involving the Main Memory 203 (see time index A). The PHOLD# signal 301 is asserted in response to the assertion of the DREQ signal 304, as shown by the arrow 310 (see time index B).
In response to the assertion of the PHOLD# signal 301, the PHLDA# signal 302 is asserted (see time index C). During the period between the time indexes B and C, the Host-PCI Bridge 202 performs various functions (i.e., flushing and disabling the CPU-to-PCI Buffer 208) to ensure that once the PCI-ISA Bridge 210 receives ownership of the PCI Bus 209, the PCI-ISA Bridge 210 has guaranteed access to the Main Memory 203. In other words, the Host-PCI Bridge 202 may prevent system deadlock conditions from occurring.
Once the PHLDA# signal 302 is asserted by the PCI arbiter 207 in the Host-PCI Bridge 202 and received by the PCI-ISA Bridge 210, the ISA Arbiter 212 asserts the DACK# signal 305 (see time index D) some time later. The assertion of the DACK# signal 305 informs the ISA DMA Agent 213 that its DMA request has been granted. Following the assertion of the DACK# signal 305, the four bytes of data written on the ISA Bus 214 (shown by waveform 306) are then written onto the PCI Bus 209 (shown by the waveform 303) before being written into the Main Memory 203. The four bytes of data shown by waveform 306 may be referred to as a Dword (e.g., 32 bit quantity). During a DMA transaction, other quantities of data may be passed to the Main Memory 203 via the PCI bus 209. When the ISA DMA Agent 213 has completed its DMA transaction over the ISA Bus 214, the DREQ signal 304 is deasserted. The deassertion of the DREQ signal 304 triggers the deassertion of the DACK# signal 305 (shown by the arrow 314). The deassertion of the DACK# signal 305 then triggers the deassertion of the PHOLD# signal 301 (shown by the arrow 316) at the time index E. Subsequently, at the time index F, the PHLDA# signal 302 is deasserted.
When the PHLDA# signal 302 is asserted (i.e., the period between the time index C and the time index F), the PCI Bus 209 may not respond to other requests to use the PCI Bus 209. For one embodiment, the latency period between the time index C and the time index D may be between 10-20 PCI clock cycles (i.e., 330-660 nanoseconds (xe2x80x9cnsxe2x80x9d)). Furthermore, the ISA Bus 214 may take approximately 6 ISA clock cycles at 120 ns each (i.e., 720 ns) to write each of the four bytes of data onto the ISA Bus 214. Thus, other components in the system may not have access to the PCI Bus 209 for approximately 1 microsecond (i.e., 33 PCI clock cycles per byte). In other words, the assertion of the PHLDA# signal ensures that the ISA DMA Agent 213 is guaranteed exclusive access of all system resources and assumes that the computer system 200 can perform no operation other than the ISA transaction from the time index C to the time index F.
By tying up the PCI Bus 209 while the ISA DMA Agent 206 is attempting to access the Main Memory 203, the overall performance of the computer system 200 may be degraded. For example, although the PCI Bus 209 may operate at 33 Megahertz (xe2x80x9cMHzxe2x80x9d) and the ISA bus 214 may operate at 8 MHz, when a DMA operation is being performed by the DMA ISA Agent 213, the PCI Bus 209 may not operate at its optimal speed due to this latency on the PCI Bus 209.
The PHOLD# and PHLDA# arbitration scheme may use a xe2x80x9cpassive releasexe2x80x9d mechanism to improve the latency on the PCI Bus 209 while the ISA DMA Agent 213 attempt to access the Main Memory 203. In general, the passive release mechanism allows the Host-PCI Bridge 202 to rearbitrate to other PCI agent s while the PCI-ISA Bridge 210 still owns the bus. More specifically, the data stream originated from the ISA Bus 214 may be partitioned into segments such that wait states may be introduced between the partitioned segments. During these wait states, rearbitration may occur such that the PCI Bus 209, the CPU 201, and the Main Memory 203 may perform other PCI Bus, CPU, and memory operations during a DMA operation performed by the ISA DMA agent 213.
FIG. 4 illustrates one embodiment of a passive release protocol implemented with the PHOLD# and PHLDA# arbitration scheme during a DMA operation by the ISA DMA Agent 213. The assertion of the DREQ signal 404 (at time index A) triggers the assertion of the PHOLD# signal 401 (at time index B). Prior to asserting the PHLDA# signal 402, the Host-PCI Bridge 202 typically flushes the CPU-to-PCI Buffer 208 in order to ensure the PCI-ISA Bridge 210 has guaranteed access to the Main Memory 203 when it becomes the PCI bus master. Thus, the PHLDA# signal 402 is asserted after the emptying end disabling of the CPU-to-PCI Buffer 208.
The passive release protocol is implemented by deasserting the PHOLD# signal 401 for a single PCI clock cycle (i.e., between time index C and D). This may be referred to as a passive release semantic. During this release period, the passive release semantic frees the PCI Bus 209, the Host Bus 204, and the Main Memory Bus 205 to allow other PCI bus masters to use the PCI Bus 209 while maintaining the CPU-to-PCI Buffer 208 flush mechanism. Between the time index D and E, PCI arbitration (xe2x80x9cPCI re-arbxe2x80x9d) begins anew. When the PCI-ISA Bridge 210 wins the PCI re-arb, and the ISA Bus 214 is ready to transfer the one-byte segment to the PCI Bus 209 (at the time index E), the one-byte segment of data is transferred across the PCI Bits 209 and written into the Main Memory 203 (between the time index E and F).
Subsequent to the transfer of the one-byte segment over the PCI Bus 209, a passive release semantic is once again issued to free up the PCI Bus 209, the Host Bus 204, and the Main Memory Bus 205 for other operations (at time index F). For one embodiment, the remaining three one-byte segments are written into the Main Memory 203 in the same manner as the first one-byte segment. When all four bytes have been transferred and the ISA DMA transaction is completed, as indicated by the ISA DMA Agent 213 deasserting the DREQ signal 404, the deassertion of the DACK# signal 405 is triggered at the time index H. Subsequently, the deassertion of the DACK# signal 405 triggers the deassertion of the PHOLD# signal 401 at the time index J. After winning the PCI re-arb that occurs between the time indexes G and I, an active release semantic is signaled by the deassertion of the PHOLD# signal 401 for a minimum of two consecutive PCI clock cycles (not shown). This active release semantic releases all of the uses and re-enables writes to the CPU-PCI Buffer 208.
Although a passive lease protocol has been incorporated into the PHOLD# and the PHLDA# arbitration scheme, the PHOLD# and PHLDA# arbitration scheme does not use the PHOLD# and PHLDA# signals to transfer information known by the Host-PCI Bridge 202 to the PCI-ISA Bridge 210. This information may be referred to as status information.
A computer system is described. The computer system includes a first bus coupled to a first bus agent, a second bus agent, and a bus arbitration circuit. The first bus agent is configured to generate a first arbitration signal and the bus arbitration circuit is configured to generate a second arbitration signal. During a transaction initiated by the first bus agent, an asserted second arbitration signal indicates the first bus agent is granted ownership of the first bus. During a transaction initiated by the second bus agent, an asserted second arbitration signal indicates a first state of a status information and a deasserted second arbitration signal indicates a second state of the status information.
A method of superimposing status information from a first bridge onto an arbitration signal received by a second bridge is described. A first arbitration signal is deasserted during at least a first clock cycle, if necessary. During at least the first clock cycle, a second arbitration signal is asserted and an address phase is provided. During at least a second clock cycle, the second arbitration signal is deasserted to indicate a first state of the status information or asserted to indicate a second state of the status information.